JPH0562463B2 - - Google Patents

Info

Publication number
JPH0562463B2
JPH0562463B2 JP58092642A JP9264283A JPH0562463B2 JP H0562463 B2 JPH0562463 B2 JP H0562463B2 JP 58092642 A JP58092642 A JP 58092642A JP 9264283 A JP9264283 A JP 9264283A JP H0562463 B2 JPH0562463 B2 JP H0562463B2
Authority
JP
Japan
Prior art keywords
film
mask material
material film
insulating film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58092642A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59217339A (ja
Inventor
Ryozo Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP9264283A priority Critical patent/JPS59217339A/ja
Publication of JPS59217339A publication Critical patent/JPS59217339A/ja
Publication of JPH0562463B2 publication Critical patent/JPH0562463B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
JP9264283A 1983-05-26 1983-05-26 半導体装置の製造方法 Granted JPS59217339A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9264283A JPS59217339A (ja) 1983-05-26 1983-05-26 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9264283A JPS59217339A (ja) 1983-05-26 1983-05-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS59217339A JPS59217339A (ja) 1984-12-07
JPH0562463B2 true JPH0562463B2 (en]) 1993-09-08

Family

ID=14060101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9264283A Granted JPS59217339A (ja) 1983-05-26 1983-05-26 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS59217339A (en])

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0763071B2 (ja) * 1984-12-14 1995-07-05 株式会社東芝 半導体装置の製造方法
US4876217A (en) * 1988-03-24 1989-10-24 Motorola Inc. Method of forming semiconductor structure isolation regions
CA2016449C (en) * 1989-07-28 1996-06-25 Steven J. Hillenius Planar isolation technique for integrated circuits
DE69004932T2 (de) * 1989-10-25 1994-05-19 Ibm Verfahren zur Herstellung breiter mit Dielektrikum gefüllter Isolationsgraben für Halbleiteranordnungen.
KR950009889B1 (ko) * 1992-08-31 1995-09-01 현대전자산업 주식회사 트렌치 기술을 이용한 반도체 장치의 소자분리영역 형성방법
KR970030214A (ko) * 1995-11-06 1997-06-26 김주용 웨이퍼 평탄화 방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320873A (en) * 1976-08-11 1978-02-25 Hitachi Ltd Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPS59217339A (ja) 1984-12-07

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